A computer processor accesses system memory to retrieve or store data within the system memory. Specifically, the processor uses the physical address of data in the memory to identify and access the data. However, the physical address where data is stored in the memory is not the address that the processor uses to index the data during internal manipulations. Rather, the processor assigns a virtual address to data being processed according to program instructions. Thus, memory accesses often require the translation of virtual addresses into physical addresses.
A conventional address translation mechanism is typically based on a translation lookaside buffer (TLB), an in-processor structure that acts as a cache for previously processed address translations. For example, in the processor instruction set architecture (ISA) of the 32-bit Intel® architecture (referred to herein as the IA-32 ISA), address translation is controlled by a TLB and a page-table hierarchy. The page-table hierarchy, which is referenced by the processor's control register CR3, is a translation data structure used to translate a virtual memory address (also referred to as a linear memory address in the context of the IA-32 ISA) into a physical memory address when paging is enabled. A page-table hierarchy includes a page directory (PD), a set of page tables (PTs), and multiple page frames (PFs). Typically, translation of a virtual memory address into a physical memory address begins with searching the TLB using either the upper 20 bits (for a 4 KB page) or the upper 10 bits (for a 4 MB page) of the virtual address. If a match is found, the upper bits of a physical page frame that are contained in the TLB are conjoined with the lower bits of the virtual address to form a physical address. If no match is found, the processor consults the page table hierarchy to determine the virtual-to-physical translation, which is then cached in the TLB.
Each entry in the PD and PTs typically includes various fields that control the accessibility of memory pages. Examples of such fields include the present (P) flag indicating whether or not the page referenced by the entry is valid, the user/supervisor (U/S) flag controlling accesses to the page referenced by the entry based on privilege level, and the read/write (R/W) flag controlling accesses based on access type (i.e., read or write)